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CS4614
Preliminary Product Bulletin
FEATURES
s 255 MIPs SLIMDTM DSP Architecture s DirectXTM 5.0 3D Positional Audio s Fat Labs Approved 64-Voice Wavetable Synthesis with Effects s NetMeeting
TM
CrystalClearTM SoundFusionTM PCI Audio Accelerator
DESCRIPTION
The CS4614 is a high performance pin-compatible upgrade to the 100-pin CS4610/11 PCI audio accelerator. With the added legacy compatibility modes, the CS4614 enables real mode DOS compatible PCI-only audio subsystems. This device, combined with application and driver software, provides a complete system solution for hardware acceleration of Windows 95(R) DirectSound(R), DirectSound3D(R), DirectInput, and Wavetable Synthesis. WDM drivers provide support for both Windows 98 and Windows NT 5.0. The CS4614 is based on the Cirrus Logic CrystalClear Stream Processor (SP) DSP core. The SP core is optimized for digital audio processing, and is powerful enough to handle complex signal processing tasks with ease. The SP core is supported by a bus mastering PCI interface and a built-in dedicated DMA engine with hardware scattergather support. These support functions ensure extremely efficient transfer of audio data streams to and from host-based memory buffers, providing a system solution with maximum performance and minimal host CPU loading. The all-digital CS4614 supports a variety of audio I/O configurations including direct connection to the CrystalClear CS4297 AC `97 Codec. PC/PCI, DDMA, and CrystalClear Legacy support provide PCI-only legacy games compatibility.
AEC Hardware Acceleration
s High Quality Hardware Sample Rate Conversion (90+ dB Dynamic Range) s PC/PCI Legacy Support s DDMA Legacy Support s CrystalClear Legacy Support (CCLSTM) s PCI 2.1 Compliant PCI Interface s 96 Stream DMA Interface with Hardware Scatter/Gather Support s PCI Power Management (D0 through D3 Hot), APM 1.2, and ACPI 1.0 Support s AC `97 2.0 Link Codec Interface s DirectInputTM Joystick Interface s MPU-401 MIDI Input/Output Interface s 3.3 V Power Supply (5 V tolerant I/O)
ORDERING INFORMATION CS4614-CM 100-pin MQFP 20x14x3.07 mm
CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM DS292PP3
Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved)
JUN `98
CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
ABSOLUTE MAXIMUM RATINGS
(PCIGND = CGND = CRYGND = 0 V, all voltages with respect to 0 V) Parameter Power Supplies Symbol PCIVDD CVDD CRYVDD VDD5REF (Note 1) Min -0.3 -45 -55 Typ Max 4.6 4.6 4.6 5.5 1.5 10 10 5.75 85 150 Unit V V V V W mA mA V C C
Total Power Dissipation Input Current per Pin, DC (Except supply pins) Output current per pin, DC Input voltage Ambient temperature (power applied) Storage temperature
(Note 2) (Note 3)
Notes: 1. Includes all power generated by AC and/or DC output loading. 2. The power supply pins are at recommended maximum values. XTALI & XTALO are at 3.6 V maximum. 3. At ambient temperatures above 70 C, total power dissipation must be limited to less than 0.4 Watts. WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(PCIGND = CGND = CRYGND = 0 V, all voltages with respect to 0 V) Parameter Power Supplies Symbol PCIVDD CVDD CRYVDD VDD5REF TA Min 3 3 3 4.75 0 Typ 3.3 3.3 3.3 5 25 Max 3.6 3.6 3.6 5.25 85 70 Unit V V V V MHz C
Internal DSP Frequency Operating Ambient Temperature
Specifications are subject to change without notice.
Windows, Windows 95, DirectSound, and DirectSound3D are registered trademarks of Microsoft Corporation. DirectInput, DirectX and NetMeeting are trademarks of Microsoft Corporation. Sound Blaster and Sound Blaster Pro are trademarks of Creative Technology, Ltd. Crystal, CrystalClear, CCLS, SLIMD and SoundFusion are trademarks of Cirrus Logic, Inc. All other names are trademarks, registered trademarks, or service marks of their respective companies.
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
AC CHARACTERISTICS (PCI SIGNAL PINS ONLY) (TA = 70 C;
PCIVDD = CVDD = CRYVDD = 3.3 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Reference levels = 1.4 V; unless otherwise noted; (Note 4)) Parameter Switching Current High (Note 5) 0 < Vout < 1.4 1.4 < Vout < 2.4 3.1 < Vout < 3.3 Switching Current Low (Note 5) Vout > 2.2 2.2 > Vout > 0.55 0.71 > Vout > 0 -5 < Vin < -1 0.4 V - 2.4 V load 2.4 V - 0.4 V load (Note 6) (Note 6) IOL 95 Vout/0.023 ICL slewr slewf
Vin + 1 - 25 + -----------------0.015
Symbol IOH
Min -44
Vout - 1.4 - 44 + --------------------------0.024
Max Note 7 Note 8 5 5
Unit mA mA
-
mA mA mA V/ns V/ns
Low Clamp Current Output rise slew rate Output fall slew rate
1 1
Notes: 4. Specifications guaranteed by characterization and not production testing. 5. Refer to V/I curves in Figure 1. Specification does not apply to PCICLK and RST# signals. Switching Current High specification does not apply to SERR# and INTA# which are open drain outputs. 6. Cumulative edge rate across specified range. Rise slew rates do not apply to open drain outputs. 7. Equation A: IOH = 11.9 * (Vout - 5.25) * (Vout + 2.45) for 3.3 V > Vout > 3.1 V 8. Equation B: IOL = 78.5 * Vout * (4.4 - Vout) for 0 V < Vout < 0.71 V
voltage 3.3
Pull Up
voltage 3.3
Pull Down AC drive point
test point 2.4 2.2 DC drive point
1.4
DC drive point
AC drive point -2 Equation A: -44 Current (mA) -176
0.55
test point 3, 6 Equation B: 95
Current (mA)
380
IOH = 11.9*(Vout-5.25)*(Vout+2.45) for 3.3V > Vout > 3.1V
IOL = 78.5*Vout*(4.4-Vout) for 0V < Vout < 0.71V
Figure 1. AC Characteristics
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CrystalClearTM SoundFusionTM PCI Audio Accelerator
DC CHARACTERISTICS (TA = 70 C; PCIVDD = CVDD = CRYVDD = 3.3 V; VDD5REF = 5 V;
PCIGND = CGND = CRYGND = 0 V; all voltages with respect to 0 V unless otherwise noted) Parameter PCI Interface Signal Pins High level input voltage Low level input voltage High level output voltage Low level output voltage High level leakage current Low level leakage current Iout = -2 mA Iout = 3 mA, 6 mA Vin = 2.7 V (Note 9) (Note 10) Symbol VIH VIL VOH VOL IIH IIL VIH VIL VOH VOL IIH IIL Min Min 2 -0.5 2.4 2.3 2 -0.5 -0.5 2.4 Typ 0.6 164 10 Typ 3.3 0 Max TBD Max 5.75 0.8 0.55 70 -70 4.0 5.75 0.8 0.8 0.4 10 -10 Unit V V V V A A V V V V V V A A Unit mA mA mA
Vin = 0.5 V(Note 10) XTALI Other Pins XTALI Other Pins (Note 11)
Non-PCI Interface Signal Pins (Except XTALO) High level input voltage
Low level input voltage High level output voltage Low level output voltage High level leakage current Low level leakage current Iout = -4 mA Iout = 4 mA Vin = 5.25 V Vin = 0
Parameter Power Supply Pins (Outputs Unloaded) Power Supply Current: VDD5REF PCIVDD/CVDD/CRYVDD Total Low Power Mode Supply Current
(Notes 4,12)
Notes: 9. The following signals are tested to 6 mA: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#, PERR#, and INTA#. All other PCI interface signals are tested to 3 mA. 10. Input leakage currents include hi-Z output leakage for all bi-directional buffers with three-state outputs. 11. For open drain pins, high level output voltage is dependent on external pull-up used and number of attached gates. 12. Typical values are given as average current with typical SP task execution and data streaming. Current values vary dramatically based on the software running on the SP.
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
PCI INTERFACE PINS (TA = 0 to 70 C; PCIVDD = CVDD = CRYVDD = 3.3 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V)
Parameter PCICLK cycle time PCICLK high time PCICLK low time PCICLK to signal valid delay - bused signals PCICLK to signal valid delay - point to point Float to active delay Active to Float delay Input Set up Time to PCICLK - bused signals Input Set up Time to PCICLK - point to point Input hold time for PCICLK Reset active time after PCICLK stable Reset active to output float delay (Note 14) (Notes 13, 14, 15) (Note 13) (Note 13) Symbol tcyc thigh tlow tval tval(p+p) ton toff tsu tsu(p+p) th trst-clk trst-off Min 30 11 11 2 2 2 7 10, 12 0 100 Max 11 12 28 40 Unit ns ns ns ns ns ns ns ns ns ns s ns
Notes: 13. For Active/Float measurements, the Hi-Z or "off" state is when the total current delivered is less than or equal to the leakage current. Specification is guaranteed by design, not production tested. 14. RST# is asserted and de-asserted asynchronously with respect to PCICLK. 15. All output drivers are asynchronously floated when RST# is active.
PCICLK
t rst-clk
RST#
t off t on
OUTPUTS Hi-Z
t rst-off
t val
OUTPUTS Valid
t su
INPUTS
Valid Input
th
Figure 2. PCI Timing Measurement Conditions
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
AC '97 SERIAL INTERFACE TIMING (TA = 0 to 70 C; PCIVDD = CVDD = CRYVDD = 3.3 V;
VDD5REF = 5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V; unless otherwise noted) Parameter ABITCLK cycle time ABITCLK rising to ASDOUT valid ASDIN valid to ABITCLK falling ASDIN hold after ABITCLK falling PCICLK rising to ARST# valid Symbol taclk tpd5 ts5 th5 tpd6 Min 78 15 5 Typ 81.4 17 10 Max 25 Unit ns ns ns ns ns
t aclk
ABITCLK ASYNC ASDOUT ASDIN ARST#
t pd5 t s5 t h5 t pd6
PCICLK
Figure 3. AC '97 Configuration Timing Diagram
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
INDEPENDENT TIMING ENVIRONMENT (TA = 0 to 70 C; PCIVDD = CVDD = CRYVDD = 3.3 V;
VDD5REF = 5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V; XTALI = 12.288 MHz; unless otherwise noted) Parameter SCLK output cycle time FSYNC output cycle time (@SCLK falling edge) SCLK falling to FSYNC transition LRCLK output cycle time (@ SCLK rising edge) SCLK rising to LRCLK transition SCLK falling to SDOUT/SDO2/SDO3 valid SDIN/SDIN2 valid to SCLK rising (SI1F2-0: 010, SI2F1-0: 00) SDIN/SDIN2 hold after SCLK rising (SI1F2-0: 010, SI2F1-0: 00) SDIN/SDIN2 valid to SCLK falling (SI1F2-0: 011, SI2F1-0: 01) SDIN/SDIN2 hold after SCLK falling (SI1F2-0: 011, SI2F1-0: 01) XTAL frequency XTALI high time XTALI low time MCLK output frequency Symbol tsclk tfsync tpd7 tlrclk tpd8 tpd9 ts6 th6 ts7 th7 Min 312 20000 -45 20000 -45 30 30 30 30 12.287 35 35 12.287 Typ 326 20833 2 20833 2 2 12.288 12.288 Max 45 45 45 12.289 12.289 Units ns ns ns ns ns ns ns ns ns ns MHz ns ns MHz
(Note 4) (Note 4) (Note 4)
tsclk SCLK tpd7 FSYNC t pd8 LRCLK tpd9 SDOUT/SD02/SD03 t s6 SDIN/SDIN2 t s7 SDIN/SDIN2 19 18 t h7 17 16 t h6 0 19 18 0 0 17 16 0 15 0 15 0 t lrclk t fsync
Figure 4. Independent Timing Configuration
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
EEPROM TIMING CHARACTERISTICS Note 4. (TA = 0 to 70 C, PCIVDD = CVDD = CRYVDD = 3.3 V; VDD5REF = 5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V; PCI clock frequency = 33 MHz; unless otherwise noted)
Parameter EECLK Low to EEDAT Data Out Valid Start Condition Hold Time EECLK Low EECLK High Start Condition Setup Time (for a Repeated Start Condition) EEDAT In Hold Time EEDAT In Setup Time EEDAT/EECLK Rise Time EEDAT/EECLK Fall Time Stop Condition Setup Time EEDAT Out Hold Time (Note 16) Symbol tAA tHD:STA tLEECLK tHEECLK tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH Min 0 5.0 10 10 5.0 0 250 5.0 0 Max 7.0 1 300 Units s s s s s s ns s ns s s
Notes: 16. Rise time on EEDAT is determined by the capacitance on the EEDAT line with all connected gates and the required external pull-up resistor.
tF
EECLK
t HEECLK
t LEECLK
tR
t HD:DAT
EEDAT (IN)
t SU:DAT
t SU:STA
EEDAT (OUT)
t HD:STA t AA t DH
t SU:STO
EEDAT (OUT)
Figure 5. EEPROM Timing
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
96-Stream DMA Controller with Hardware Scatter/Gather PC/PCI & CCLS Legacy
Parameter RAM
AC '97 2.0 Interface
Sample RAM Program RAM Program ROM Coefficient ROM PLL Clock SLIMD SP Core GPIO
PCI Interface
MPU-401 MIDI Interface
Joystick Interface
Figure 6. CS4614 Block Diagram
OVERVIEW
The CS4614 is a high performance audio accelerator DSP for the PCI bus. This device, combined with application and driver software, provides a complete system solution for cost effective acceleration of Windows DirectSound, Direct-Sound3D, DirectInput, MIDI playback via Wavetable Synthesis with reverberation and chorus effects processing, and more. The CS4614 is compatible with the CS4610/11 with the following added features: * AC `97 Interface now 2.0 compatible * CrystalClear Legacy Support * PC/PCI Legacy Support * DDMA Legacy Support There are three main functional blocks within the CS4614: the Stream Processor, the PCI Interface, and the DMA Engine. A block diagram of the CS4614 device is shown in Figure 6. The Stream Processor (SP) is a high speed custom Digital Signal Processor (DSP) core specifically designed for audio signal processing. The Stream Processor is capable of running a number of different signal processing algorithms simultaneously. This high concurrency capability is valuable for applications such as immersive 3D games, which may play a number of DirectSound streams, a number of DirectSound3D streams, and a MIDI music sequence simultaneously.
Separate RAM memories are included on-chip for the SP program code (PROGRAM RAM), parameter data (PARAMETER RAM), and audio sample data (SAMPLE RAM). Two ROM memories store coefficients for sample rate conversion and audio decompression algorithms (COEFFICIENT ROM) and common algorithm code (PROGRAM ROM). The RAM-based DSP architecture of the CS4614 ensures maximum system flexibility. The software function/feature mix can be adapted to meet the requirements of a variety of different applications, such as DirectXTM games or DOS applications. This RAM-based architecture also provides a means for future system upgrades, allowing the addition of new or upgraded functionality through software updates. The CS4614 provides an extremely efficient bus mastering interface to the PCI bus. The PCI Interface function allows economical burst mode transfers of audio data between host system memory buffers and the CS4614 device. Program code and parameter data are also transferred to the CS4614 over the PCI interface. The DMA Engine provides dedicated hardware to manage transfer of up to 96 concurrent audio/data streams to and from host memory buffers. The DMA Engine provides hardware scatter-gather support, allowing simple buffer allocation and
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
management. This implementation improves system efficiency by minimizing the number of host interrupts. The CS4614 supports a variety of audio I/O configurations including a CS4297 CrystalClear AC '97 Codec. The system's flexibility is further enhanced by the inclusion of a bi-directional serial MIDI port, a joystick port, a hardware volume control interface, and a serial data port which allows connection of an optional external EEPROM device. In both motherboard and add-in card designs, CCLS and DDMA provide support for legacy games by providing a hardware interface that supports a Sound Blaster Pro compatible interface, as well as support for FM, MPU-401, and joystick interfaces. These hardware interfaces provide PCIonly games compatibility for real-mode DOS and Windows DOS-box support. For motherboard designs, PC/PCI can be used by connecting the PCGNT# and PCREQ# pins to the appropriate pins on the south bridge motherboard chip. The PC/PCI interface is compliant with Intel's PC/PCI spec. (version 1.2). The BIOS must enable the PC/PCI mechanism at boot time on both the CS4614 and the south bridge.
Stream Processor DSP Core
The CS4614 Stream Processor (SP) is a custom DSP core design which is optimized for processing and synthesizing digital audio data streams. The SP features a Somewhat Long Instruction Multiple Data (SLIMD) modified dual Harvard architecture. The device uses a 40-bit instruction word and operates on 32-bit data words. The SP includes two Multiply-Accumulate (MAC) blocks and one 16bit Arithmetic and Logic Unit (ALU). The SP core is conservatively rated at 255 Million Instructions per second (255 MIPS) when running at a 85 MHz internal clock speed. The MAC units perform dual 20-bit by 16-bit multiplies and have 40-bit accumulators, providing higher quality than typical 16-bit DSP architectures. A programmable Phase Locked Loop (PLL) circuit generates the high frequency internal SP clock from a lower frequency input clock. The input to the PLL may be from a crystal oscillator circuit or the serial port clock ABITCLK/SCLK. Clock control circuitry allows gating of clocks to various internal functional blocks to conserve power during power conservation modes, as well as during normal modes of operation when no tasks are being executed.
SYSTEM ARCHITECTURES
A typical system diagram depicting connection of the CS4614 to the CrystalClear CS4297 AC '97 Codec is given in Figure 7. All analog audio inputs and outputs are connected to the CS4297. Audio data is passed between the CS4297 and the CS4614 over the serial AC-Link. The CS4614 provides a hardware interface for connection of a joystick and MIDI devices.
HOST INTERFACE
The CS4614 host interface is comprised of two separate interface blocks which are memory mapped into host address space. The interface blocks can be located anywhere in the host 32-bit physical address space. The interface block locations are defined by the addresses programmed into the two Base Address Registers in the PCI Configuration Space. These base addresses are normally set up by the system's Plug and Play BIOS. The first interface block (located by Base Address 0) is a 4 kByte register block containing general purpose configuration, control, and status registers for the device. The second interface block (located by Base Address 1) is a 1 MByte block which maps all of the internal RAM memories (SP Program RAM, Pa-
Legacy Support
Legacy games are supported by CrystalClear Legacy Support (CCLS), DDMA, or by the PC/PCI interface.
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CrystalClearTM SoundFusionTM PCI Audio Accelerator
CPU
North Bridge
Host Memory
PCI Bus
South Bridge
Audio Out
CS4614 Accelerator
CS4297 Audio In
PC/PCI (if used)
Figure 7. AC `97 Codec Interface
rameter RAM, and Sample RAM) into host memory space. This allows the host to directly peek and poke RAM locations on the device. The relationship between the Base Address Registers in the CS4614 PCI Configuration Space and the host memory map is depicted in Figure 8. The bus mastering PCI bus interface complies with the PCI Local Bus Specification (version 2.1).
or memory), Configuration Read (from CS4614 configuration registers), Configuration Write (to CS4614 configuration registers), Memory Read Multiple (aliased to Memory Read), Memory Read Line (aliased to Memory Read), and the Memory Write and Invalidate (aliased to Memory Write) transfer cycles. The I/O Read, I/O Write, Interrupt Acknowledge, Special Cycles, and Dual Address Cycle transactions are not supported. As Bus Master, the CS4614 generates the Memory Read Multiple and Memory Write transactions. The Memory Read, Configuration Read, Configuration Write, Memory Read Line, Memory Write
Direct I/O Registers (Memory Mapped, 4 kByte)
PCI bus transactions
As a target of a PCI bus transaction, the CS4614 supports the Memory Read (from internal registers or memory), Memory Write (to internal registers
Device PCI Config. Space 00h 04h 08h 0Ch 10h 14h Device ID / Vendor ID Status / Command Class Code / Revision Misc. Control Base Address Register 0 Base Address Register 1 Direct Memory Interface (Memory Mapped, 1 MByte)
Figure 8. Host Interface Base Address Registers
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CrystalClearTM SoundFusionTM PCI Audio Accelerator
and Invalidate, I/O Read, I/O Write, Interrupt Acknowledge, Special Cycles, and Dual Address Cycle transactions are not generated. The PCI bus transactions supported by the CS4614 device are summarized in Table 1. Note that no Target Abort conditions are signalled by the device. Byte, Word, and Doubleword transfers are supported for Configuration Space accesses. Only Doubleword transfers are supported for Register or Memory area accesses. Bursting is not supported for host-initiated transfers to/from the CS4614 internal register space, RAM memory space, or PCI configuration space (disconnect after first phase of transaction is completed).
Configuration Space
The content and format of the PCI Configuration Space is given in Table 2.
Initiator Host
Target Registers (BA0)
Type Mem Write
PCI Dir
In Out In Out In Out Out In
Host Host Host Host Host DMA DMA
Registers (BA0) Memories (BA1) Memories (BA1) Config Space 1 Config Space 1 Host System Host System
Mem Read Mem Write Mem Read Config Write Config Read Mem Write Mem Read
Table 1. PCI Interface Transaction Summary Byte 3 Device ID: R/O, 6003h Status Register, bits 15-0: Bit 15 Detected Parity Error: Error Bit Bit 14 Signalled SERR: Error Bit Bit 13 Received Master Abort: Error Bit Bit 12 Received Target Abort: Error Bit Bit 11 Signalled Target Abort: Error Bit Bit 10-9 DEVSEL Timing: R/O, 01b (medium) Bit 8 Data Parity Error Detected: Error Bit Bit 7 Fast Back to Back Capable: R/O 0 Bit 6 User Definable Features: R/O 0 Bit 5 66MHz Bus: R/O 0 Bit 4 New Capabilities: R/O 1 Bit 3-0Reserved: R/O 0000 Reset Status State: 0210h Write of 1 to any error bit position clears it. Byte 2 Byte 1 Vendor ID: R/O, 1013h Command Register, bits 15-0: Bit 15-10: Reserved, R/O 0 Bit 9 Fast B2B Enable: R/O 0 Bit 8 SERR Enable: R/W, default 0 Bit 7 Wait Control: R/O 0 Bit 6 Parity Error Response: R/W, default 0 Bit 5 VGA Palette Snoop: R/O 0 Bit 4 MWI Enable: R/O 0 Bit 3 Special Cycles: R/O 0 Bit 2 Bus Master Enable: R/W, default 0 Bit 1 Memory Space Enable: R/W, default 0 Bit 0 IO Space Enable: R/O 0 Byte 0 Offset 00h 04h
Table 2. PCI Configuration Space
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CrystalClearTM SoundFusionTM PCI Audio Accelerator
Byte 3
Byte 2
Byte 1
Byte 0 Revision ID: R/O 01h Cache Line Size: R/O 0
Offset 08h 0Ch
Class Code: R/O 040100h Class 04h (multimedia device), Sub-class 01h (audio), Interface 00h BIST: R/O 0 Header Type: Bit 7: R/O 0 Bit 6-0: R/O 0 (type 0) Latency Timer: Bit 7-3: R/W,default 0 Bit 2-0: R/O 0
Base Address Register 0 Device Control Register space, memory mapped. 4 kByte size Bit 31-12: R/W, default 0. Compare address for register space accesses Bit 11 - 4: R/O 0, specifies 4 kByte size Bit 3: R/O 0, Not Prefetchable (Cacheable) Bit 2-1: R/O 00, Location Type - Anywhere in 32 bit address space Bit 0: R/O 0, Memory space indicator Base Address Register 1 Device Memory Array mapped into host system memory space, 1 MByte size Bit 31-20: R/W, default 0. Compare address for memory array accesses Bit 19 - 4: R/O 0, specifies 1 MByte size Bit 3: R/O 0, Not Prefetchable (Cacheable) Bit 2-1: R/O 00, Location Type - Anywhere in 32 bit address space Bit 0: R/O 0, Memory space indicator Base Address Register 2: R/O 00000000h, Unused Base Address Register 3: R/O 00000000h, Unused Base Address Register 4: R/O 00000000h, Unused Base Address Register 5: R/O 00000000h, Unused Cardbus CIS Pointer: R/O 00000000h, Unused Subsystem ID R/O 0000h if EXTEE not present, otherwise R/W, loaded from EEPROM Subsystem Vendor ID R/O 0000h if EXTEE not present, otherwise R/W, loaded from EEPROM
10h
14h
18h 1Ch 20h 24h 28h 2Ch
Expansion ROM Base Address: R/O 00000000h, Unused Reserved: R/O 00000000h Reserved: R/O 00000000h Max_Lat: R/O 18h 24 x 0.25uS = 6 uS Min_Gnt: R/O 04h 4 x 0.25uS = 1uS Interrupt Pin: R/O 01h, INTA used Interrupt Line: R/W, default 0
30h 34h 38h 3Ch
Table 2. PCI Configuration Space (cont.)
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CrystalClearTM SoundFusionTM PCI Audio Accelerator
Byte 3 PMC Bit 15: PME# from D3cold: R/O 0 Bit 14: PME# from D3hot: R/O 1 Bit 13: PME# from D2: R/O 1 Bit 12: PME# from D1: R/O 1 Bit 11: PME# from D0: R/O 1 Bit 10: D2 support: R/O 1 Bit 9: D1 support: R/O 1 Bit 8-6: Reserved: R/O 000 Bit 5: Device Specific init: R/O 1 Bit 4: Auxiliary power: R/O 0 Bit 3: PME# clock: R/O 1 Bit 2-0: Version: R/O 001
Byte 2
Byte 1
Byte 0
Offset
Next Item Pointer: R/O 0h
Capability ID: R/O 1h
40h
Data: R/O 0
PMCSR_BSE: R/O 0
PMCSR Bit 15: PME# status: R/W 0 Bit 14-13: Data scale: R/O 00 Bit 12-9: Data select: R/O 0000 Bit 8: PME_En: R/W 0 Bit 7-2: Reserved: R/O 000000 Bit 1-0: Power state: R/W 00
44h
Table 2. PCI Configuration Space (cont.)
Subsystem Vendor ID Fields
The Subsystem ID and Subsystem Vendor ID fields in the PCI Configuration Space default to value 0000h unless an external EEPROM device is detected or unless the host has written to the appropriate internal register to program the values.
pointer passes the mid-point or wraps around. Virtual channels are also used for message passing between the CS4614 and the host.
SERIAL PORT CONFIGURATIONS
A flexible serial audio interface is provided which allows connection to external Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters (DACs) or Codecs (combined ADC and DAC functions) in several different configurations. The serial audio interface includes a primary input/output port with dedicated serial data pins (SDIN, SDOUT), two auxiliary audio output ports (SDO2, SDO3) which share pins with the joystick interface button input functions, and one auxiliary audio input port (SDIN2). Each of these digital audio input and output pins carry two channels of audio data. These two channels may comprise the left and right channels of a stereo audio signal, or two independent monaural audio signals. Each digital audio channel is internally buffered through a 16 sample x 20-bit FIFO. The data format
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Interrupt Signal
The CS4614 PCI Interface includes an interrupt controller function which receives interrupt requests from multiple sources within the CS4614 device, and presents a single interrupt line (INTA) to the host system. Interrupt control registers in the CS4614 provide the host interrupt service routine with the ability to identify the source of the interrupt and to clear the interrupt sources. In the CS4614, the single external interrupt is expanded by the use of "virtual channels". Each data stream which is read from or written to a modular buffer is assigned a virtual channel number. This virtual channel number is signalled by the DMA subsystem anytime the associated modulo buffer
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CrystalClearTM SoundFusionTM PCI Audio Accelerator
ABITCLK ASYNC ASDOUT ASDIN ARST#
CS4614
12.288 MHz 48 kHz
BIT_CLK
SDATA_OUT SDATA_IN RESET#
24.576 MHz
CS4297
MIDIIN MIDIOUT JACX, JACY, JBCX, JBCY JAB1, JAB2, JBB1, JBB2
Figure 9. AC `97 Codec Connection Diagram
Joystick/ MIDI Port
for the serial digital audio ports varies depending on the configuration. The primary configuration includes a CS4614 plus a CS4297. The CS4614 communicates with the CS4297 over the AC-link as specified in the Intel(R) Audio Codec `97 Specification (version 1.03) with support for the 2.0 extensions. A block diagram for the AC'97 Controller configuration is given in Figure 7. The signal connections between the CS4614 and the AC '97 Codec are indicated in Figure 9. In this configuration, the AC '97 Codec is the timing master for the digital audio link. The ASDOUT output supports data transmission on all ten possible sample slots (output slots 3 - 12). The ASDIN input supports receiving of audio sample data on all input sample slots (input slots 3 - 12). The SDO2 and SDO3 serial outputs are not supported in this configuration.
MIDI Port
In the AC '97 controller configuration, a bi-directional MIDI interface is provided to allow connection of external MIDI devices. The MIDI interface includes 16-byte FIFOs for the MIDI transmit and receive paths.
Joystick Port
In the AC '97 controller configuration, a joystick port is provided. The joystick port supports four "coordinate" channels and four "button" channels. The coordinate channels provide joystick positional information to the host, and the button channels provide user button event information. The joystick interface is capable of operating in the traditional "polled" mode, but also provides a "hardware accelerated" mode of operation wherein internal counters are provided to assist the host with coordinate position determination. The Joystick schematic is illustrated in Figure 10.
DS292PP3
Analog Interface
SYNC
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
+5 V
DSP
4.7 k 4.7 k
1 9 2 10
2.2 k 2.2 k 5.6 nF 1 nF 1 nF
JAB1 JBB1 JACX JBCX
5.6 nF
3 11 4 12
4.7 k 4.7 k
JBCY JACY JBB2 JAB2
4.7 k
2.2 k 2.2 k
5 13 6 14 7 15
MIDIOUT MIDIIN
5.6 nF 5.6 nF
1 nF
1 nF
8
Figure 10. Joystick Logic
EEPROM INTERFACE
The EEPROM configuration interface allows the connection of an optional external EEPROM device to provide power-up configuration information. The external EEPROM is not required for proper operation; however, in some applications power-up configuration settings other than the default values may be required to support specific Operating System compatibility requirements. After a hardware reset, an internal state machine in the CS4614 will automatically detect the presence of an external EEPROM device and load the Subsystem ID and Subsystem Vendor ID fields, along with two bytes of general configuration information, into internal registers. At power-up, the CS4614 will attempt to read from the external device, and will check the data received from the device for a valid signature header. If the header data is invalid, the data transfer is aborted. After power-
up, the host can read or write from/to the EEPROM device by accessing specific registers in the CS4614. Cirrus Logic provides software to read and write the EEPROM. The two-wire interface for the optional external EEPROM device is depicted in Figure 11. During data transfers, the data line (EEDAT) can change state only while the clock signal (EECLK) is low. A state change of the data line while the clock signal is high indicates a start or stop condition to the EEPROM device.
SLIMD SP Core
4.7 k EEDAT EECLK 2-wire Serial EEPROM
Figure 11. External EEPROM Connection
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator The EEPROM device read access sequence is shown in the Figure 12. The timing follows that of a random read sequence. The CS4614 first performs a "dummy" write operation, then generates a start condition followed by the slave device address and the byte address of zero. The CS4614 always begins access at byte address zero and continues access a byte at a time, using a sequential read, until all needed bytes in the EEPROM are read. Since only 7 bytes are needed, the smallest EEPROM available will suffice.
GENERAL PURPOSE I/O PINS
Many of the CS4614 signal pins are internally multiplexed to serve different functions depending on the environment in which the device is being used. Several of the CS4614 signal pins may be used as general purpose I/O pins when not required for other specific functions in a given application.
DSP
Bank Part Write Address Start Part Read StartAddress Address
S 1 0 1 0 0 0 0 0 A 0 0 0 0 0 0 0 0 AS 1 0 1 0 0 0 0 1 A
No AcknowledgeAcknowledge Stop
Data A Data 1P
EEPROM
Acknowledge
Data
Figure 12. EEPROM Read Sequence
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
PIN DESCRIPTION
PCIVDD[7] PCIGND[7] AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] PCIGND[6] PCIVDD[6] C/BE[0]# AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] PCIVDD[5] TEST JACX JACY JBCX JBCY JAB1/SDO2 JAB2/SDO3 JBB1/LRCLK JBB2/MCLK MIDIIN CVDD[2] CGND[2] MIDIOUT CVDD[3] CGND[3] SDIN2/GPIO CGND[4] CVDD[4] CRYVDD VOLUP/XTALI VOLDN/XTALO CRYGND VDD5REF ABITCLK/SCLK ASDOUT/SDOUT ASDIN/SDIN ASYNC/FSYNC ARST# EECLK/PCREQ# EEDAT/PCGNT# 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
18
INTA# RST# PCICLK GNT# REQ# PCIVDD[0] PCIGND[0] AD[31] AD[30] AD[29] AD[28] AD[27] PCIGND[1] PCIVDD[1] AD[26] AD[25] AD[24] C/BE[3]# IDSEL PCIVDD[2]
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
PCIGND[5] AD[14] AD[15] C/BE[1]# PAR SERR# PERR# STOP# PCIGND[4] PCIVDD[4] DEVSEL# CVDD[0] CGND[0] TRDY# IRDY# FRAME# C/BE[2]# CGND[1] CVDD[1] AD[16] AD[17] AD[18] PCIVDD[3] PCIGND[3] AD[19] AD[20] AD[21] AD[22] AD[23] PCIGND[2]
CS4614-CM
100-pin MQFP
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
A `#' sign suffix on a pin names indicates an active-low signal.
PCI Interface
AD[31:0] - Address/Data Bus, I/O, Pins 88-92, 95-97, 2-6, 9-11, 28-29, 32-37, 41-48 These pins form the multiplexed address / data bus for the PCI interface. C/BE[3:0]# - Command Type / Byte Enables, I/O, Pins 98, 14, 27, 38 These four pins are the multiplexed command / byte enables for the PCI interface. During the address phase of a transaction, these pins indicate cycle type. During the data phases of a transaction, active low byte enable information for the current data phase is indicated. These pins are inputs during slave operation and they are outputs during bus mastering operation. PAR - Parity, I/O, Pin 26 The Parity pin indicates even parity across AD[31:0] and C_BE[3:0] for both address and data phases. The signal is delayed one PCI clock from either the address or data phase for which parity is generated. FRAME# - Cycle Frame, I/O, Pin 15 FRAME# is driven by the current PCI bus master to indicate the beginning and duration of a transaction. IRDY# - Initiator Ready, I/O, Pin 16 IRDY# is driven by the current PCI bus master to indicate that as the initiator it is ready to transmit or receive data (complete the current data phase). TRDY# - Target Ready, I/O, Pin 17 TRDY# is driven by the current PCI bus target to indicate that as the target device it is ready to transmit or receive data (complete the current data phase). STOP# - Transition Stop, I/O, Pin 23 STOP# is driven active by the current PCI bus target to indicate a request to the master to stop the current transaction. IDSEL - Initialize Device Select, Input, Pin 99 IDSEL is used as a chip select during PCI configuration read and write cycles. DEVSEL# - Device Select, I/O, Pin 20 DEVSEL# is driven by the PCI bus target device to indicate that it has decoded the address of the current transaction as its own chip select range.
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
REQ# - Master Request, Three-State Output, Pin 85 REQ# indicates to the system arbiter that this device is requesting access to the PCI bus. This pin is high-impedance when RST# is active. GNT# - Master Grant, Input, Pin 84 GNT# is driven by the system arbiter to indicate to the device that the PCI bus has been granted. PERR# - Parity Error, I/O, Pin 24 PERR# is used for reporting data parity errors on the PCI bus. SERR# - System Error, Open Drain Output, Pin 25 SERR# is used for reporting address parity errors and other catastrophic system errors. INTA# - Host Interrupt A (for SP), Open Drain Output, Pin 81 INTA# is the level triggered interrupt pin dedicated to servicing internal device interrupt sources. PCICLK - PCI Bus Clock, Input, Pin 83 PCICLK is the PCI bus clock for timing all PCI transactions. All PCI synchronous signals are generated and sampled relative to the rising edge of this clock. RST# - PCI Device Reset, Pin 82 RST# is the PCI bus master reset. VDD5REF: Clean 5 V Power Supply, Pin 73 VDD5REF is the power connection pin for the 5 V PCI pseudo supply for the PCI bus drivers. The internal core logic runs on 3.3 Volts. This pin enables the PCI interface to support and be tolerant of 5 Volt signals. Must be connected to +5 Volts. PCIVDD[7:0] - PCI Bus Driver Power Supply, Pins 50, 39, 31, 21, 8, 100, 94, 86 PCIVDD pins are the PCI driver power supply pins. These pins must have a nominal +3.3 Volts. PCIGND[7:0] - PCI Bus Driver Ground Pins, Pins 49, 40, 30, 22, 7, 1, 93, 87 PCIGND pins are the PCI driver ground reference pins.
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
External Interface Pins
TEST - Test Mode Strap, Input, Pin 51 This pin is sampled at reset for test mode entry. If it is high at reset, test mode is enabled. This pin must be pulled to ground for normal operation. EEDAT/PCGNT# - EEPROM Data Line / PC/PCI Grant, I/O, Pin 80 For expansion card designs, this is the data line for external serial EEPROM containing device configuration data. When used with an external EEPROM, a 4.7 k pullup resistor is required. In motherboard designs using PC/PCI, this pin is the PC/PCI serialized grant input. In designs with neither of the above requirements, this pin can be used as a general purpose input or open drain output (GPIO2). EECLK/PCREQ# - EEPROM Clock Line / PC/PCI Request, Output, Pin 79 For expansion card designs, this is the clock line for external serial EEPROM containing device configuration data. In motherboard designs using PC/PCI, this pin is the PC/PCI serialized request output. In designs with neither of the above requirements, this pin can be used as a general purpose output pin (GPOUT). SDIN2/GPIO - Serial Data Input 2 / General Purpose I/O Pin, I/O, Pin 66 This dual function pin defaults as a general purpose I/O pin. In non-AC '97 system configurations, this pin can function as a second stereo digital data input pin if enabled. VOLUP/XTALI - Volume-Up Button / Crystal In, Input, Pin 70 This dual function pin is either the volume-up button control input or the crystal oscillator input pin, depending on system configuration. This pin may also be used as a general purpose input if its primary function is not needed. VOLDN/XTALO - Volume-Down Button / Crystal Output, I/O, Pin 71 This dual function pin is either the volume-down button control input or the crystal oscillator output pin, depending on system configuration. This pin may also be used as a general purpose input if its primary function is not needed.
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator Clock / Miscellaneous
CRYVDD - Crystal & PLL Power Supply, Pin 69 Power pin for crystal oscillator and internal phase locked loop. This pin must be connected to a nominal +3.3 Volts. CRYGND - Crystal & PLL Ground Supply, Pin 72 Ground pin for crystal oscillator and internal phase locked loop. JACX, JACY, JBCX, JBCY - Joystick A and B X/Y Coordinates, I/O, Pins 52, 53, 54, 55 These pins are the 4 axis coordinates for the joystick port. These pins may also be used as a general purpose inputs or open drain outputs if their primary function is not needed. JAB1/SDO2 - Joystick A Button 1 / Serial Data Output 2, I/O, Pin 56 This dual function pin defaults as JAB1 (button 1 input for joystick A). In non-AC '97 system configurations, this pin can function as a second stereo digital data output pin if enabled. This pin can also be a general purpose polled input if a second data output stream is not required. JAB2/SDO3 - Joystick A Button 2 / Serial Data Output 3, I/O, Pin 57 This dual function pin defaults as JAB2 (button 2 input for joystick A). In non-AC '97 system configurations, this pin can function as a third stereo digital data output pin if enabled. This pin can also be a general purpose polled input if a third data output stream is not required. JBB1/LRCLK - Joystick B Button 1 / L/R Framing Clock, I/O, Pin 58 This dual function pin defaults as JBB1 (button 1 input for joystick B). In non-AC '97 system configurations, this pin can function as a left/right framing clock output pin for SDO2 and SDO3. This pin can also be used as a general purpose polled input if alternate data output streams are not required. JBB2/MCLK - Joystick B Button 2 / Master Clock, I/O, Pin 59 This dual function pin defaults as JBB2 (button 2 input for joystick B). In non-AC '97 system configurations, this pin can function as a master (256x sample rate) output clock if enabled. This pin can also be used as a general purpose polled input if alternate data output streams are not required. MIDIIN - MIDI Data Input, Pin 60 This is the serial input pin for the internal MIDI port. MIDIOUT - MIDI Data Output, Pin 63 This is the serial output pin for the internal MIDI port. CVDD[4:0] - Core Power Supply, Pins 68, 64, 61, 12, 19 Core / Stream Processor power pins. These pins must be connected to a nominal +3.3 Volts.
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator CGND[4:0] - Core Ground Supply, Pins 67, 65, 62, 13, 18 Core / Stream Processor ground reference pins. Serial Codec Interface ABITCLK/SCLK - AC `97 Bit Clock / Serial Audio Data Clock, I/O, Pin 74 Master timing clock for serial audio data. In AC '97 configurations, this pin is an input which drives the timing for the AC '97 interface, along with providing the source clock for the CS4614. In external DAC configurations, it an output, providing the serial bit clock. ASYNC/FSYNC - AC `97 Frame Sync / Serial Audio Frame Sync, I/O, Pin 77 Framing clock for serial audio data. In AC '97 configurations, this pin is an output which indicates the framing for the AC '97 link. In external DAC configurations, this pin is an FSYNC output, providing the left/right framing clock. ASDOUT/SDOUT - AC `97 Data Out / Serial Audio Data Out, Output, Pin 75 AC `97 serial data out / Serial audio output data. ARST# - AC `97 Reset, Output, Pin 78 AC '97 link reset pin. This pin also functions as a general purpose reset output in non-AC '97 configurations and will follow RST# to ground, but must be forced high by software. ASDIN/SDIN - AC `97 Data In / Serial Audio Data In, Input, Pin 76 Serial audio input data.
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CS4614
CrystalClearTM SoundFusionTM PCI Audio Accelerator
PACKAGE OUTLINE
`M' Package 100-pin MQFP
E E1
D D1
1
e
B A A1
L
INCHES DIM A A1 B D D1 E E1 e MIN 0.000 0.010 0.009 0.667 0.547 0.904 0.783 0.022 0.000 0.018 MAX 0.134 0.014 0.015 0.687 0.555 0.923 0.791 0.030 7.000 0.030
L
MILLIMETERS MIN MAX 0.000 3.400 0.250 0.350 0.220 0.380 16.950 17.450 13.900 14.100 22.950 23.450 19.900 20.100 0.550 0.750 0.000 7.00 0.450 0.750
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CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM
DS292PP3

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